Joining several processors in parallel increases processing capacity. Typically, any number from two to eight processors may be joined in parallel. Generally, multiple parallel processors are joined together on a shared bus. FIG. 1 illustrates a four processor (4P; architecture used in conjunction with a shared bus. Four processors, Processor 1, Processor 2, Processor 3, and Processor 4, connect to a shared bus, which in turn connects to the Northbridge chipset. The Northbridge chipset further connects to the Southbridge chipset and external memory. For example, a Pentium™ processor may employ the shared bus architecture illustrated in FIG. 1. However, a point-to point architecture, typically, provides a higher bandwidth than does a shared bus architecture.
In a shared bus architecture, multiple devices all share the same bus and must follow an order and protocol to use the bus. In contrast, a point-to-point bus architecture provides an uninterrupted connection between two separate devices. Thus, in general, a point-to-point bus creates a higher bandwidth between two separate devices. A higher bandwidth can have the beneficial effect of yielding an increased performance from a single processor or group of processors. For example, if a 48-bit connection exists between two devices, then transactions occur between the two device three times faster than if only a 16-bit connection exists between the two devices. However, a point-to-point bus architecture may have a disadvantage because the architecture provides an uninterrupted connection between two separate devices. Thus, if at any given time, light transfers of information occur between the two devices, then the excess bandwidth capacity is essentially wasted.
For example, if a customer is using his or her computer system to run both a workstation application and a server application, then the customer may not be achieving peak performance from the hardware in his computer system. In a server application a heavy exchange of information occurs between processors. Thus, the manufacturer creates a high bandwidth connection between each processor in the system. Yet, if for example a customer wants to use his computer system for an application, which involves a heavy exchange of information between processors and a chipset, such as a workstation application, then the manufacturer creates a high bandwidth connection between each processor and the chip in the system. However, if the customer has a computer system which has a high bandwidth connection between the processor(s) and the chipset, but chooses to currently run a server application on this system, then the customer may suffer poor performance from the server application and waste the excess bandwidth between the chipset and processor(s).
While the invention is subject to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and will herein be described in detail. The invention should be understood to not be limited to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.